Present day digital circuit applications are becoming increasing sophisticated as the range of applications for these circuits increases. As one example of this, analog-to-digital converters (ADCs) utilize sampling circuitry that samples an analog input signal at points in time, and then converts the samples to digital values to create a digital signal. The use of ADCs is common for certain types of applications, which can involve receiving an input signal or input data represented by an analog signal, and then converting the analog signal to a digital signal for further processing in a digital form. Many other applications of digital data transfer also exist.
There is a need for high-speed digital transfers in many types of modern data handling applications including wireless infrastructure (e.g., GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, WiFi, TD-SCDMA, etc.), transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and military/aerospace applications. For example, the continuing increase in sophistication of technologies for processing audio, video, or other types of analog signals (e.g., from various types of sensors) has caused an accompanying need to increase the technical capabilities of ADCs. In addition, a similar increase is warranted in the technical capabilities and performance of the analog interface and the digital interface circuitry that interacts with ADCs. Many applications require increasingly higher numbers of data inputs and outputs between high-speed data converters and other devices (e.g., field-programmable gate arrays (FPGAs), digital signal processors (DSP), etc.).
The synchronization of transferred data between high-speed data converters and other devices becomes increasingly more difficult, as the number of data inputs and outputs interfacing between the devices increases. For example, when data is transferred from an ADC to another device, it may be necessary to implement any number of high-speed serial channels, each over a separate physical interface, where the physical interfaces are separated. Data generated at the core of an ADC should be routed to separate physical interfaces. This routing can cause problems with signal latency. Hence, certain links can have multiple parallel high-speed serial channels for a potential aggregate data link (e.g., 100 GB/s), where minimum latency is desired on the link. Each high-speed serial channel can be a physical interface (PHY) and each physical interface channel can be physically separated by millimeters on a corresponding die. The data generated in the core can be routed to eight locations (e.g., separated by as much as 5 mm).
Additionally, there are timing differences in the arrival of data at the different interfaces. Clock signals at each of the physical interfaces could be skewed relative to one another, causing problems in that the timing of output data on each of the physical interfaces will be different. Each core-to-physical interface data handoff can have different timing and, further, metastability will be a concern if a globally routed physical interface clock is used. Metastability generally describes the behavior of certain physical systems that can exist in long-lived states that are less stable than the system's most stable state.
One solution to the synchronization problem has been to use a first-in-first-out structure to ensure the data handoff on the interface. However, the first-in-first-out structure creates an additional expense in latency. Another solution involves delivering the data directly from the core to the physical interface boundary and, thereby, the system accepts the potential metastability at the core-to-physical interface boundary. Hence, each of these solutions has drawbacks and tradeoffs. Therefore, in ADCs (along with any other appropriate applications of digital data transfer), it would be desirable to have a solution for interfacing between a digital core and a physical interface that could reduce both latency and metastability problems in data transfers between devices.
Overview
The present disclosure relates generally to an apparatus and a method for synchronizing data transfer from a digital core to a physical interface (PHY). The method and apparatus can be embodied in circuitry that interfaces an analog-digital-converter (ADC) core to a physical interface. In one embodiment, the core has its own ADC core clock and the physical interface has its own phase-locked-loop (PLL). In one example implementation, the PHY section contains a baudrate PLL, as discussed below. In general terms, there is no inherent phase relationship between the ADC core clock and the clock of the physical interface.
A core reset signal can be synchronized to the core clock and then oversampled at the physical interface by a clock generated from the PLL clock. This can be used to generate a physical interface sampled reset signal. The sampled reset signal can be used to synchronize a physical interface clock (at a rate of baudrate/M) with the core clock (at a rate baudrate/M, to within a known margin). The physical interface clock can then be used to clock data into the physical interface from the core outputs that are being clocked by the core clock.
In another embodiment, the circuitry can be implemented such that a reset signal in the core is clocked into a core macro using a macro clock, which is at a rate (e.g., baudrate/M) sufficient to generate a macro clock synchronized reset. The macro clock synchronized reset is then oversampled with a physical interface clock, which is generated from the PLL clock (and which is at a rate (baudrate/N), where N<M) to generate a physical interface sampled reset signal. The sampling of the synchronized reset signal can generate a physical interface sampled reset signal that has a known time relationship with the reset signal and the macro clock. In one example embodiment, the circuitry is configured so that when the physical interface sampled reset signal is in a first state, local physical interface clock generators do not toggle and, instead, stay in a predetermined state. When the physical interface sampled reset signal moves to a second state, the local physical interface clock generators start in a known state. The physical interface clock generators that generate the physical interface data clock at a rate of baudrate/M are programmable in x unit increment (UI) steps, where a UI is defined as the duration of a serial bit. Through use of the oversampling technique, a physical interface baudrate/M clock is produced with a known phase relationship (e.g., accurate within 2 UI) to the macro baudrate/M clock. The physical interface baudrate/M clock can be used to clock data into the local physical interface from the macro outputs that are clocked by the macro baudrate/M clock.
In one example embodiment, the circuitry is configured such that a reset signal for the core is clocked into a core macro flop using the macro clock (e.g., at a rate baudrate/40) to generate a macro clock synchronized reset. The macro clock synchronized reset is then oversampled with a physical interface clock, which is generated from the PLL clock (e.g., at a rate baudrate/2) to generate a physical interface sampled reset signal. The sampling of the synchronized reset signal can generate a physical interface sampled reset signal that has a known time relationship with the reset signal of the core and the macro clock. The circuitry is configured so that when the physical interface sampled reset signal is in a first state, local physical interface clock generators do not toggle and, instead, stay in a known state. When the physical interface sampled reset signal moves to a second state, the local physical interface clock generators start in a known state. The physical interface clock generators generate the physical interface data clock at a rate of baudrate/40, which is programmable in eight UI steps. Through use of the oversampling technique, a local physical interface baudrate/40 clock is produced with a known phase relationship accurate within 2 UI to the macro baudrate/40 clock. The physical interface baudrate/40 clock can be used to clock data into the local physical interface from the macro data flops that are being clocked by the macro baudrate/40 clock. In alternative embodiments, the clock rates and relative clock rates can be varied, along with other design parameters, as necessary to give different phase relationships.